Method of making an EPROM memory cell
US4849369A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 20, 1987 |
| Grant date | Jul 18, 1989 |
| Priority date | — |
| Expiry date | Aug 20, 2007 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/681
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An a MIS integrated circuit, such as an EPROM memory cell integrated onto a semiconductor substrate comprises (a) memory points which are insulated from one another and have in each case a stack of materials formed from a first insulant in contact with the substrate, first and second gates separated from one another by a second insulant, the first gate being in contact with the first insulant, a source and a drain formed in the substrate on either side of the stack of gates, and a channel, whose length is oriented according to a first direction Y, (b) first metal lines parallel to the first direction for applying electric signals to said stacks and (c) second conductor lines parallel to a second direction X perpendicular to the first direction and produced on the drains for applying electric signals to said drains. A process for making the circuit is also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.