Method and apparatus for generating a data sampling clock locked to a baud clock contained in a data signal
US4849703A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 1, 1988 |
| Grant date | Jul 18, 1989 |
| Priority date | — |
| Expiry date | Apr 1, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0331
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An improved baud clock recovery, synchronization and data sampling circuit for a modem. A CODEC (41) samples the incoming signal at a rate determined by the sample clock output of a presettable counter (236). The sampled signal is then squared (231) and bandpass filtered (232) to provide a recovered baud clock. A detector (233) signals the positive going zero-crossing points of the recovered baud clock. A lead/lag calculator (234) determines which of the signal samples is nearest the zero-crossing point. The calculator (234) then determines whether this and every subsequent 12th sampling point leads or lags the zero-crossing point by inspecting the sign of the recovered baud clock and adjusts the preset inputs of the counter (236) to cause the sample points to occur at the zero-crossing point.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.