Fully differential non-linear amplifier
US4849708A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 1988 |
| Grant date | Jul 18, 1989 |
| Priority date | — |
| Expiry date | Jun 30, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06G7/25
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A fully differential non-linear amplifier includes an operational amplifier (12), a first input resistor (R1), a second input resistor (R2), a first feedback resistor (R3), a second feedback resistor (R4), a first clamping network (CN1), and a second clamping network (CN2). The first clamping network (CN1) is formed of a first P-channel clamping transistor (P10) and a first N-channel clamping transistor (N10). The second clamping network (CN2) is formed of a second P-channel clamping transistor (P12) and a second N-channel clamping transistor (N12). The gates of the first and second P-channel clamping transistors (P10, P12) are connected to receive a P-bias signal. The gates of the first and second N-channel clamping transistors (N10, N12) are connected to receive a N-bias signal. The non-linear amplifier clamps its differential output signal to a constant voltage level independent of variations in process and temperature.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.