Analogue to digital converter
US4849759A · kind A · utility
13Cited by
7References
15Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 21, 1987 |
| Grant date | Jul 18, 1989 |
| Priority date | — |
| Expiry date | Dec 21, 2007 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/167
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In a half-flash analogue to digital converter (ADC) for balanced signals, d.c. offset compensation is provided by means of two negative feedback arrangements 510 and 520. A first compensating signal LOFF is the time-average of the output of the middle comparator MC17 of the coarse converter stage and provides compensation of offsets in the most significant bits (MSB) of the output. A second compensating signal COFF is generated by an additional comparator MC34 to effect compensation of offsets re-introduced when a difference amplifier 404 forms the residual signal V.sub.LSB for the input to the fine converter stage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.