Read channel architecture for processing read head signals
US4849834A · kind A · utility
Inventor
Key dates
| Filing date | Aug 7, 1986 |
| Grant date | Jul 18, 1989 |
| Priority date | — |
| Expiry date | Aug 7, 2006 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11B20/10009
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A read channel circuit includes a high frequency filter and a pair of differentiators, one of which is a high resolution differentiator and the other of which is a low resolution differentiator intentionally adjusted to perform its differentiation function imperfectly. Comparators serve as zero crossing detectors for the high and low resoltuion signals. The comparator for the low resoltuion path provides the data input to a flip-flop. The comparator for the high resolution path has its output processed by an exclusive OR gate and a delay circuit before being applied to the clock input of the flip-flop. The high-resolution and low-resolution paths are combined in the flip-flop, whose digital output faithfully reproduces the binary information received by the read head by deriving timing from the high-resoltuion path and by effectively discriminating against artifacts in the read head's signal which would result in spurious transitions in the read channel's output were it not for the imperfect differentiation provided in the low-resolution path.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.