Computer address modification system with optional DMA paging
US4849875A · kind A · utility
39Cited by
19References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 10, 1987 |
| Grant date | Jul 18, 1989 |
| Priority date | — |
| Expiry date | Aug 10, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/206
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer system includes a computer address modification system that is advantageously coupled in a bus network to selectively translate memory address data in 16K blocks and provide DMA page addresses in 16K blocks which may match the 16K memory address blocks. The modification system includes a mapping RAM selectively providing translated addresses to enable addresses in a 16 megabyte extended address space. The modification system also includes a page register storing for each addressable 16K block of data for each DMA channel a page address within the extended address space.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.