Digital delay unit with interleaved memory
US4849937A · kind A · utility
163Cited by
6References
4Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 17, 1988 |
| Grant date | Jul 18, 1989 |
| Priority date | — |
| Expiry date | Mar 17, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/04
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A first memory cell array (84) has an even address space and a second memory cell array 94 has an odd address space. The memory cell arrays (84, 94) are alternately accessed by even address signals generated from an address counter (81) and odd address signals generated from an address counter (91) so that the data stored in the memory cell arrays are alternately read while new input data are written in the accessed memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.