Semiconductor memorizing device
US4849939A · kind A · utility
11Cited by
2References
23Claims
0Family size
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Inventors
Key dates
| Filing date | Sep 24, 1987 |
| Grant date | Jul 18, 1989 |
| Priority date | — |
| Expiry date | Sep 24, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory having a memory array, a first and a second selection line which are connected to a memory cell, and a selection means which selects either one of the selection lines. The selection means includes a selection circuit which optionally selects the first selection line or the second selection line when an address signal corresponding to the first selection line is aligned with a predetermined address signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.