Clock holdover circuit
US4849993A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 10, 1987 |
| Grant date | Jul 18, 1989 |
| Priority date | — |
| Expiry date | Dec 10, 2007 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/145
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present invention provides a clock holdover circuit which will provide a replacement clock signal within predetermined parameters independently of time and temperature variations. The circuit of the present invention has only a single component which is time and temperature dependent. By selecting the components parameters to be within the desired tolerances, the accuracy of the circuit is maintained. In the present invention, digital circuitry is combined with an accurate local crystal frequency source to provide a replacement clock signal. The present invention allows phase consistency upon loss of a reference clock signal as well as on return of the reference clock signal. A reference clock signal is phase locked to a VCO to produce a desired output. The frequency of the output is compared to a local frequency standard to generate an offset frequency used to control a frequency synthesizer. The offset frequency is digitally stored. Upon loss of the reference clock signal, the stored offset frequency is used to drive the frequency synthesizer along with the local frequency standard so as to provide an acceptable replacement clock signal. The frequency comparator, storage, and…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.