Phase perturbation compensation system
US4849996A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 22, 1988 |
| Grant date | Jul 18, 1989 |
| Priority date | — |
| Expiry date | Sep 22, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/03133
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
In a phase perturbation compensation system for use in a data modem receiver, the signal from an equalizer is fed to a phase and amplitude correction circuit which is connected to a decision circuit providing a data output signal and a phase error output signal which is applied to a phase jitter compensation determination circuit. The phase jitter compensation determination circuit includes a tapped delay line the output taps of which are applied to multipliers fed with adaptive weighting coefficients to provide values which are summed to provide a phase error prediction signal. The weighting coefficients are generated in integrator circuits which include respective delays. The values generated in the delays during an initial training sequence and stored in a storage device are retrieved for use in subsequent training segments, whereby fast phase jitter adaptation is achieved and hence stort training sequences can be utilized.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.