Process for the production of a memory cell
US4851365A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 8, 1988 |
| Grant date | Jul 25, 1989 |
| Priority date | — |
| Expiry date | Jul 8, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/681
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process for producing a memory cell, particularly of the ROM or EPROM type, having a matrix of memory points, each memory point comprising a source, a drain and at least one gate. In a first step, a mask is produced for defining the position of stacks in which the gates are produced. This is followed by the production of the sources and the drains during second and third successive and independent steps. The second step consists of an etching operation, a doping operation and an insulating operation, while the third step involves an etching operation and a doping operation. The operation is completed by producing the conductive lines connecting the drains of the memory points aligned in a direction Y.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.