Schottky-clamped transistor logic buffer circuit
US4851715A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 20, 1988 |
| Grant date | Jul 25, 1989 |
| Priority date | — |
| Expiry date | Dec 20, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0846
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A high speed interstage STL buffer (27) is disclosed having a low threshold and high driving capability. A first Schottky-clamped grounded emitter transistor (28) receives input signals through a Schottky steering diode (38) and inverts the input signal. The input signal is applied in parallel through a Schottky steering diode (20) to a second Schottky-clamped grounded emitter transistor (12). The collector (22) of the second transistor (12) provides an output of the buffer (27) for driving load current in one direction with respect to the buffer output. A third transistor (40) connected as an emitter follower has the emitter (42) thereof connected to the buffer output for driving load currents in the other direction. The base (46) of the emitter follower transistor (40) is coupled by a Schottky steering diode (50) to the collector (32) of the first transistor (28). The steering diodes (20, 38, 50) have a forward threshold voltage less than that of the Schottky-barrier diodes used to clamp the base-collector junctions of the first and second transistors (28, 12).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.