Central processor unit for digital data processing system including write buffer management mechanism
US4851991A · kind A · utility
25Cited by
5References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 24, 1987 |
| Grant date | Jul 25, 1989 |
| Priority date | — |
| Expiry date | Feb 24, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/32
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor for use in a digital data processing system including a main memory and a write buffer for buffering write data and associated addresses from the processor for storage in the storage locations identified by the associated addresses in the main memory. In response to selection occurances, such as a context switch, which cannot be detected outside of the processor, the processor asserts a signal which enables the write buffer to transfer all of its contents to the main memory. The write buffer, in turn, disables the processor while it is transferring data to the main memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.