Cache move-in bypass
US4851993A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 20, 1987 |
| Grant date | Jul 25, 1989 |
| Priority date | — |
| Expiry date | Apr 20, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0888
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Bypassing of data from a main storage unit to an instruction and operand processing unit around an intermediate storage unit improves performance in a data processing system. The instruction and operand processing unit supplies requests for operands to the intermediate storage unit or cache. If the line is missing from the cache, the request operand is retrieved from the main storage unit. A bypass data path is connected between the main storage unit, prior to error detecting means in the cache, and the instruction and operand processing unit for transferring requested operands to the instruction and operand processing unit directly. Control, coupled to receive requests for operands and to the instruction and operand processing unit, signals the instruction and operand processing unit to receive the requested operands from the bypass data path when the data includes a requested operand.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.