Precharge circuit for use in a semiconductor memory device
US4852064A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 16, 1988 |
| Grant date | Jul 25, 1989 |
| Priority date | — |
| Expiry date | Jun 16, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A precharge circuit for use in a static random access memory is disclosed two step bit line pair precharging scheme in a precharge cycle performed prior to a read operation. The first precharging step is performed via each drain-source path of N-channel MOS transistor pair to the corresponding bit lines in response to a first pulse generated by the write enable signal and the following second precharging step is performed via means for precharging more dominantly than the transistor pair in response to a second pulse generated by the address transition detection circuit. Owing to the off-state of the N-channel MOS transistor pair in a read operation after a write operation, high speed read operation is obtained.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.