Expandable digital switching matrix with fault-tolerance and minimum delay time
US4852085A · kind A · utility
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4Claims
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Key dates
| Filing date | May 2, 1986 |
| Grant date | Jul 25, 1989 |
| Priority date | — |
| Expiry date | May 2, 2006 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04Q11/04
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
In a telecommunications switching system, the physical switching matrix is constructed in modular parts for easy expansion. A complete set of switching lines in one direction is cross-indexed with a partial set of switching lines in the other direction, and modular expansion is allowed by adding further partial sets of switching lines to further complete the matrix. Minimum bit delay is accomplished by routing all data bits through at most two data buffers on their transmission through the switch.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.