Error correction method using Reed-Solomon code
US4852099A · kind A · utility
21Cited by
6References
2Claims
0Family size
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Key dates
| Filing date | Feb 2, 1988 |
| Grant date | Jul 25, 1989 |
| Priority date | — |
| Expiry date | Feb 2, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/15
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In an error correction method using Reed-Solomon code when the error correction is performed by using the result of the multiplication of a syndrome and an error location, another syndrome is added to thereby form a new syndrome. By repetitively executing this procedure, the error vector is obtained by a small number of arithmetic operations relative to a known procedure, thereby performing error correction by the so-called erasure correction technique. Then, by calculating another error vector using the first calculated error vector, the number of arithmetic operation times can be even further reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.