Error detection and correction scheme for main storage unit
US4852100A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 11, 1987 |
| Grant date | Jul 25, 1989 |
| Priority date | — |
| Expiry date | Jun 11, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides an apparatus for reporting errors in data stored in a memory apparatus of a data processor, comprising: first means for storing multiple digital first signals; second means for storing said multiple digital first signals and adapted for storing at least one digital second signal; third means for transmitting said multiple digital first signals substantially from said first means to said second means; fourth means for providing said at least one digital second signal, in the course of the transmitting of said first signals by said third means, in response to an occurrence of one or more errors in one or more of said multiple digital first signals; fifth means for transmitting said multiple digital first signals substantially from said second means to said first means; and sixth means adapted for receiving said at least one digital second signal in the course of the transmitting of said multiple digital first signals by said fifth means and for providing at least one third signal in response to an occurrence of said at least one digital second signal. ECC codes are generated and applied over a plurality of distinct checking blocks in each flow of data i…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.