Bus expander with logic for virtualizing single cache control into dual channels with separate directories and prefetch for different processors
US4853846A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 29, 1986 |
| Grant date | Aug 1, 1989 |
| Priority date | — |
| Expiry date | Jul 29, 2006 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/6022
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Control logic for controlling references to a cache (24) including a cache directory (62) which is capable of being configured into a plurality of ways, each way including tag and valid-bit storage for associatively searching the directory (62) for cache data-array addresses. A cache-configuration register and control logic (64) splits the cache directory (62) into two logical directories, one directory for controlling requests from a first processor and the other directory for controlling requests from a second processor. A prefetch buffer (63) is provided along with a prefetch control register for splitting the prefetch buffer into two logical channels, a first channel for handling prefetches associated with requests from the first processor, and a second channel for handling prefetches associated with requests from the second processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.