Binary adder having a fixed operand and parallel-serial binary multiplier incorporating such an adder
US4853887A · kind A · utility
14Cited by
6References
7Claims
0Family size
Inventors
Key dates
| Filing date | Sep 11, 1987 |
| Grant date | Aug 1, 1989 |
| Priority date | — |
| Expiry date | Sep 11, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/3876
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Binary adder having a fixed operand and a parallel-serial binary multiplier incorporating such an adder. The multiplier comprises a dedicated adder, whose elements (transistors, logic gates, etc.) are wired to incorporate the value of the fixed operand B. The non-fixed operand D is applied in serial form to the control input of a multiplexer. The multiplier also comprises an accumulator-shift register for storing a partial result A of the multiplication. As a function of the state of the multiplexer, the register receives A or A+B.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.