Automatic test generator for logic devices
US4853928A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 28, 1987 |
| Grant date | Aug 1, 1989 |
| Priority date | — |
| Expiry date | Aug 28, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318371
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An algebraic recursion process is defined to solve test conditions for sequential and combinatorial logic devices. The process is shown to be effective in identifying external pin faults, and is valid for in-circuit test conditions. Since only external pin faults are considered, there is no issue of the correspondence of Boolean products to the internal architecture of the device. Processes to identify the fault detection equation and initialization sequence are described and an effective minimization process presented. Functions simple enough to be implemented by logic networks fall within a range which is computationally tractable by the process of the invention.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.