Fabrication of a GaAs short channel lightly doped drain MESFET
US4855246A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 21, 1988 |
| Grant date | Aug 8, 1989 |
| Priority date | — |
| Expiry date | Sep 21, 2008 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/161
Abstract
Disclosed is a self-aligned GaAs, lightly doped drain metal-semiconductor field effect transistor. In one embodiment, the device consists of a shallow n.sup.- active channel region formed on a GaAs substrate, a Schottky gate overlying the n.sup.- region and highly doped and deep n.sup.+ source and drain regions formed on either side of the gate. In the channel region between the gate edges and the source/drain are positioned n-type source/drain extensions which have an intermediate depth and doping concentration to minimize the device series resistance, suppress short channel effects and permit channel length reduction to submicron levels. In a second embodiment, p-type pockets are provided under the source/drain extensions to better control the device threshold voltage and further reduce the channel length. In terms of the method of fabrication of the first embodiment, starting with a GaAs substrate an n.sup.- semiconductor layer is formed in the device active region. Next, a Schottky gate is formed in direct contact with the n.sup.- layer. Next, a dielectric layer is deposited and reactive ion etched (RIE), forming gate sidewalls. Then, n-type source/drain extensions are formed f…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.