Wafer scale integration semiconductor device having improved chip power-supply connection arrangement
US4855613A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 15, 1988 |
| Grant date | Aug 8, 1989 |
| Priority date | — |
| Expiry date | Jan 15, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/213
Abstract
A plurality of RAM chips, a V.sub.CC power supply terminal and a V.sub.SS power supply terminal are all formed on one wafer. Each of the RAM chips comprises an MOS circuit comprising a V.sub.CC power supply line and a V.sub.SS power supply line, a power supply terminal and a ground terminal. The ground terminal is connected to the V.sub.SS power supply line through an N channel MOS transistor, and the power supply terminal is connected to the V.sub.CC power supply line. The MOS transistor has a gate connected to a power supply terminal through a fuse element. The power supply terminals and the ground terminals in the plurality of RAM chips are connected to the V.sub.CC power supply terminal and the V.sub.SS power supply terminal, respectively, by aluminum interconnections. When a power-supply voltage is applied between the V.sub.CC power supply terminal and the V.sub.SS power supply terminal, the MOS transistor in each of the RAM chips is turned on, so that the power-supply voltage is supplied to the MOS circuit in each of the RAM chips. When a fuse element in any of the RAM chips is disconnected, the MOS transistor in the RAM chip is turned off, so that the power-supply voltage is…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.