Low-power bipolar-CMOS interface circuit
US4855624A · kind A · utility
6Cited by
7References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 2, 1988 |
| Grant date | Aug 8, 1989 |
| Priority date | — |
| Expiry date | Feb 2, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00384
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A biCMOS interface circuit receives a plurality of incoming signals at a first level and supplies a plurality of output signals at a second level. The interface circuit establishes control voltages which are used to maintain an identical trip point in each of a plurality of translator circuits. Generally, the trip point is set at midway between the "high" and the "low" levels of the incoming logic signal. The control voltages assure reliable performance over a wide operating environment.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.