Differential amplifier circuit
US4855686A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 2, 1988 |
| Grant date | Aug 8, 1989 |
| Priority date | — |
| Expiry date | Jun 2, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/45674
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Disclosed is a differential amplifier circuit which includes a first NPN transistor, a second NPN transistor, a current source connected to the emitters of the first and second NPN transistors, a first PNP load transistor having a collector connected to the collector of the first NPN transistor, a second PNP load transistor having a collector coupled to the collector of the second NPN transistor, and an FET having a gate connected to the collector of the first NPN transistor, and a source connected to the bases of the first and second PNP load transistors. A DC input current of the FET is substantially zero, and is designed to absorb a current corresponding to the gate potential of the FET, from the bases of the first and second PNP load transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.