Electronic vehicle speed control system having analog and digital memory circuits
US4855918A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 28, 1986 |
| Grant date | Aug 8, 1989 |
| Priority date | — |
| Expiry date | Aug 28, 2006 |
Classification
- Technology area (CPC B)Performing Operations; Transporting
- CPC primaryB60K31/107
- WIPO fieldTransport
- WIPO sectorMechanical engineering
Abstract
An improved electronic system for automatically maintaining the actual speed of a vehicle at or near a desired speed is disclosed. The system includes means for generating electrical signals representing both the actual and desired speeds of the vehicle. The desired speed signal generating means includes a digital memory circuit and an analog memory circuit. The digital memory circuit and the analog memory circuit are provided to generate and store electrical signals which are representative of the desired speed of the vehicle during different phases of operation of the system. The digital memory circuit is utilized to supply the desired speed signal to the comparison circuit during normal operation of the system. The analog memory circuit is utilized to supply the desired speed signal to the comparison circuit when the resume or accerleration features of the system are activated. The outputs of the digital memory circuit and the analog memory circuit are both connected to a memory buffer circuit. The memory buffer circuit feeds only the lesser one of the desired speed signals stored in the digital and analog memory circuits to a comparison circuit, where it is compared with the ac…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.