Dual port memory circuit
US4855959A · kind A · utility
34Cited by
5References
4Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 6, 1987 |
| Grant date | Aug 8, 1989 |
| Priority date | — |
| Expiry date | Jul 6, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1075
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An improved dual port memory circuit in which data transfer from the memory array to the data register can be performed without interrupting the serial access in the serial access port is shown. The memory circuit is featured in that first and second transfer circuits are provided between a first half and the second remaining half of the columns, and first and second registers, respectively. One of the transfer circuits which is connected to the non-accessed data register is enabled while serial access to the accessed data register is maintained.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.