Duplicated circuit arrangement for fast transmission and repairability
US4856000A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 8, 1987 |
| Grant date | Aug 8, 1989 |
| Priority date | — |
| Expiry date | Sep 8, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Duplicated circuit arrangement comprising a main processor (30) and its P bit data bus (44), and two identical redundant devices (21:22), each device is comprised of a processing element (23;35) performing the same task in parallel on a P bits word, and send/receive circuits (24,25;36,37) controlled by the main processor through lines (SR11 to SR22) to transmit said word to and from said main processor. For each device, the send/receive circuits are split into two parts. Send/receive circuit of the first device (21) is split in two parts (24, 25); the first part (24) handles the P/2 Most Significant Bits (MSB's) and the second part (25) handles the P/2 Less Significant Bits (LSB's). In normal operation, during the transmission step, only the first part (24) is allowed to send bits on one half (33) of the data bus (44). Symmetrically send/receive circuit of the second device (22), is also split in two parts (36, 37); the first section (36) handles the P/2 Most Significant bits (MSB's) and the second part (37) handles the P/2 Less Significant Bits Z(LSB's); only the second part (37) is allowed to send bits on the other half (34) of the data bus (44). Therefore, the data bus driving e…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.