Parallel binary adder having grouped stages including dynamic logic to increase carry propagation speed
US4858167A · kind A · utility
2Cited by
6References
3Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 14, 1988 |
| Grant date | Aug 15, 1989 |
| Priority date | — |
| Expiry date | Dec 14, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/506
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A binary adder circuit is described using dynamic transistor logic in which for high speed carry propagation the adder stages are grouped in pairs or larger numbers and additional dynamic logic means is provided in each group to control a single transistor connected in series in the carry propagation path over the group. The transistors used in the specific embodiments are MOS transistors, but some or all of these could be replaced by junction FET's or bipolar transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.