Bit line charge sensing apparatus having CMOS threshold voltage compensation
US4858195A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 30, 1987 |
| Grant date | Aug 15, 1989 |
| Priority date | — |
| Expiry date | Mar 30, 2007 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/011
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An apparatus for sensing an electric charge appearing on at least one bit line of a memory cell comprises a pair of P-channel MOS (Metal Oxide Semiconductor) transistors whose sources are commonly connected, a pair of N-channel MOS (Metal Oxide Semiconductor) transistors whose sources are commonly connected, both pairs of the PMOS and NMOS transistors carrying out latch operations according to control signals supplied to their sources to sense the electric charge appearing on either a first or second bit line. In at least one of the pairs of PMOS and NMOS transistors, the gate of each MOS transistor is connected to either the first or second bit line via a capacitor, a first switching element is disposed between the drain of each MOS transistor and gate thereof, and a second switching element is disposed between the drain of each MOS transistor and a junction to either the first or second bit line. When control voltages applied to both sources of the PMOS transistors and NMOS transistors are changed and the switching elements are switched over during a precharge interval and sensing operation interval, the capacitors store voltages according to the respective threshold voltages of …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.