Quadword boundary cache system
US4860192A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 3, 1986 |
| Grant date | Aug 22, 1989 |
| Priority date | — |
| Expiry date | Oct 3, 2006 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/1054
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a cache memory system, multiple-word boundary registers, multiple-word line registers, and a multiple-word boundary detector system provide accelerated access of data contained within the cache memory within the multiple-word boundaries, and provides for effective prefetch of sequentially ascending locations of stored data from the cache memory. In an illustrated embodiment, the cache memory stores four words per addressable line of cache storage, and accordingly quad-word boundary registers determine boundary limits on quad-words, quad-word line registers store, in parallel, a selected line from the cache memory, and a quad-word boundary detector system determines when to prefetch the next set of quad-words from the cache memory for storage in the quad-word line registers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.