Binary tree parallel processor
US4860201A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 2, 1986 |
| Grant date | Aug 22, 1989 |
| Priority date | — |
| Expiry date | Sep 2, 2006 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A plurality of parallel processing elements are connected in a binary tree configuration, with each processing element except those in the highest and lowest levels being in communication with a single parent processing element as well as first and second (or left and right) child processing elements. Each processing element comprises a processor, a read/write or random access memory, and an input/output (I/O) device. The I/O device provides interfacing between each processing element and its parent and children processing elements so as to provide significant improvements in propagation speeds through the binary tree. The I/O device allows the presently preferred embodiment of the invention to be clocked at 12 megahertz, producing in the case of a tree of 1023 processors, each having an average instruction cycle time of 1.8 .mu.s, a system with a raw computational throughput of approximately 570 million instructions per second. The I/O device communicates data and queries from the root processing element to all other N processing elements in the array in one processor instruction cycle instead of in O(log.sub.2 N) processor instruction cycles as in prior art binary tree arrays. Pr…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.