Non-volatile memory incremental counting system
US4860228A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 24, 1987 |
| Grant date | Aug 22, 1989 |
| Priority date | — |
| Expiry date | Feb 24, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01C22/02
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Disclosed is a technique for storing a count of incrementally increasing data exclusively in EEPROM using semaphores to avoid significant losses, as a result of power downs, greater than a single least significant bit in accuracy. The disclosed embodiment includes a first EEPROM register, comprised of 256 bits, for storing 256 incremental count increases, each bit is used to record an incremental count increase. A pair of 16 bit EEPROM registers is provided for incrementally storing updated count information in response to the first EEPROM register overflowing. Semaphores are provided for indicating whether or not the incrementally increasing count information has been at least partially stored in the pair of registers. Once an overflow from the first register is detected, the semaphores are checked to determine in what stage the update to the pair of registers was left (in case of power down). In response to the semaphore information, the overflow is stored in the pair of registers for a complete update of the count, and the semaphores are appropriately updated to so indicate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.