Multizone array processor implementing two sided zone buffers with each side being dynamically configured as a working or I/O side
US4860249A · kind A · utility
8Cited by
7References
2Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 4, 1985 |
| Grant date | Aug 22, 1989 |
| Priority date | — |
| Expiry date | Oct 4, 2005 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/8007
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A reconfigurable processor array (RPA) for performing high speed operations on data arrays and eliminating I/O bottleneck. The array memory has a working side for storing arrays to be processed during a given array operation, and an I/O side for loading an array to be used during a subsequent operation and downloading an array resulting from a preceding operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.