Vertical blanking status flag indicator system
US4860251A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 17, 1986 |
| Grant date | Aug 22, 1989 |
| Priority date | — |
| Expiry date | Nov 17, 2006 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2360/18
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An improved display system which includes a central processing unit (CPU) coupled to a display utilizing vertical blanking intervals. A frame buffer memory is coupled to the CPU for storing data representative of color indices for each display pixel. The frame buffer is further coupled to look-up tables (LUTs) for storing color values which are provided through digital/analog converters (DACs) to the display. The CPU updates the contents of the frame buffer and/or LUTs during the vertical blanking interval of the display. A "first half" status flag is provided to the CPU at the beginning of each vertical blanking interval. This status flag remains true until one half of the period has elapsed. A "too late" status flag is also provided at the initiation of the interval which remains low until the end of the vertical blanking interval. The CPU may, based upon when the memory update begins relative to the status flags, determine whether or not to continue the update or terminate until the next vertical blanking interval. Accordingly, system efficiency is significantly increased and display integrity preserved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.