Reset circuit for electrically isolated circuits communicating via uart
US4860289A · kind A · utility
13Cited by
10References
24Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 19, 1987 |
| Grant date | Aug 22, 1989 |
| Priority date | — |
| Expiry date | Oct 19, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/0757
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A simplified master controller or outguard circuit monitors and controls a plurality of separate slave, or inguard, circuits. Only a single watchdog circuit is provided on the outguard arrangement, with simplified timers being provided on each inguard arrangement to generate a direct hardware reset signal for local microprocessors in the inguard circuits using existing serial communication lines. A break signal generated by the watchdog in the outguard circuit is detected and, without interpretation, converted to the reset signal for the inguard circuit in synchronism with operation of the outguard circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.