Error protected central control unit of a switching system and method of operation of its memory configuration

US4860333A · kind A · utility

Assignee

• Oread Laboratories · US

Inventors

• Rudolf Bitzinger · Munich, DE
• Walter Engl · Feldkirchen-Westerham, DE
• Siegfried Humml · Penzberg, DE
• Klaus Schreier · Penzberg, DE

Key dates

• Filing date: Mar 11, 1987
• Grant date: Aug 22, 1989
• Expiry date: Mar 11, 2007

Classification

• Technology area (CPC H): Electricity
• CPC primary: H04Q3/5455
• WIPO field: Telecommunications
• WIPO sector: Electrical engineering

Abstract

A multiprocessor central control unit a switching system with a main memory (CMY) including, aside from a tolerable timing slip, synchronously parallel operated memory block pairs (MB3a/MB3b) during normal operation. The main memory (CMY), together with the central processors (BP, CP . . . IOC . . . ), is connected to a central bus system (B:CMY0/CMY1). The data stored in parallel in the memory blocks of the memory block pairs (e.g., MB3a/MB3b) are EDC-protected. The processors have access to the memory block pairs (e.g. MB3a/MB3b). Upon the occurrence of a multiple error in an indicated second memory block (e.g., MB3b) of a memory block pair (MB3a/MB3b), the second memory block (MB3b) is isolated from the bus system (B:CMY0/B:CMY1) via an automatic memory configuration. The first memory block (MB3a) then performs the read and/or write operations alone, while from time to time the data stored in the second memory block (MB3b) are corrected by reading out of the first memory block (MB3a) and writing into the second memory block (MB3b), but during a concurrent write operation to the first memory block (MB3a) the data to be entered is also immediately written into the second memory bl…