Entry point address circuit for microcode rom
US4864535A · kind A · utility
4Cited by
10References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 6, 1985 |
| Grant date | Sep 5, 1989 |
| Priority date | — |
| Expiry date | Dec 6, 2005 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multiplexer (76) for coupling selected instruction word bits to a microcode memory (22) as entry point addresses. The multiplexer (76) receives sixteen bits from an instruction word register (10) and, for normal word formats, couples the opcode (40) portion unchanged to the memory (22) as an entry point address. For special instruction word formats, various bits of the instruction word fields form an entry point address, while other bits are modified and coupled to memory (22) as column addresses to access selected memory sections.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.