Bipolar ram having no write recovery time
US4864540A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 11, 1988 |
| Grant date | Sep 5, 1989 |
| Priority date | — |
| Expiry date | Feb 11, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/416
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A bipolar random access memory having no write recovery time. During a data write operation, while the memory state of the memory cell is being shifted, a data bypass circuit sets a sense latch in the sense amplifier to store the new state to which the memory cell is being set. To prevent the sense latch from being shifted by transient write recovery currents charging bit line parasitic capacitances following the data write operation, a read/write transmission circuit isolates the sense amplifier from the bit lines, diverts current from the sense amplifier to a source of high voltage to charge the parasitic capacitances, and then realigns the sense amplifier to the bit lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.