Loop status verification system
US4864598A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 20, 1988 |
| Grant date | Sep 5, 1989 |
| Priority date | — |
| Expiry date | Jul 20, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04M11/04
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A system is disclosed for verifying the integrity of each one of a number of communication paths, illustratively telephone subscriber loops, that runs between a near end location, illustratively a telephone central office, and corresponding remote ("far end") location(s). This system utilizes circuitry, such as a line verification module, that is located at the far end of the path to detect one or more conditions thereat (e.g. loop current and loop voltage) that are indicative of normal operation of the path, e.g. proper on-hook and off-hook conditions. As long as the path is normally operating at the far end, this circuitry would then transmit a test signal, e.g. a selected one of a number of sub-audible frequencies, over the path to the near end. This test signal is chosen to be substantially transparent to normal communication (e.g. local telephone company signalling and transmission frequencies) occurring over that path. Central office monitoring circuitry, illustratively containing a line test unit and a controller, would be connected to the path at its near end. This monitoring circuitry would detect any cessation or unexpected change in the test signal (i.e. a mismatch again…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.