Data limiter having current controlled response time
US4866261A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 16, 1988 |
| Grant date | Sep 12, 1989 |
| Priority date | — |
| Expiry date | Sep 16, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/1295
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A data limiter in a paging receiver for converting an analog signal to a digital signal, the data limiter having a variable time constant. The data limiter includes an amplifying circuit and an integrating circuit. The amplifying circuit, being responsive to the analog input signal generated from a receiving circuit of the paging receiver, generates a reference signal depending upon a variable bias current input to the amplifying circuit. The integrating circuit, being responsive to the reference signal, generates a comparison signal depending upon a variable gain input. The amplifying circuit responsive to the comparison signal compares the comparison signal to the input signal for generating a digital output signal. A processing circuit of the paging receiver generates a first control signal for modifying the variable bias current input and a second output signal for modifying the variable gain input. Additionally, the processing circuit generates a third control signal being applied to the integrating circuit for effecting a storage of the comparison signal in the integrating circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.