Wafer scale integration
US4866501A · kind A · utility
56Cited by
4References
14Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 16, 1985 |
| Grant date | Sep 12, 1989 |
| Priority date | — |
| Expiry date | Dec 16, 2005 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15787
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A circuit package comprises at least one IC chip bonded directly in a hole provided in a wafer such that the surface of the chip and the surface of the wafer are in the same plane thereby accommodating TAB bonding of the chip to bonding pads provided on the wafer. The structure can include multilayer circuitry on the wafer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.