Module for packaging semiconductor integrated circuit chips on a base substrate
US4866507A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 19, 1986 |
| Grant date | Sep 12, 1989 |
| Priority date | — |
| Expiry date | May 19, 2006 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit chip packaging structure, preferably having a semiconductor base substrate, i.e., silicon or gallium arsenide, alternating insulation and conductive layers on the base structure, at least two conductive layers being patterned into thin film wiring (i.e., thin film copper of approximately 5 microns), semiconductor integrated circuit chips connected to the upper-most patterned conductive layer, and means to connected the packaging structure to the next level of packaging (i.e., board or card). The thin film wiring layers typically each having coplanar ground, power and signal lines, with at least one power or ground line existing between coplanar signal lines to minimize cross talk. To facilitate efficient power distribution, lines of specific power levels of the patterned planes are connected to lines of the same power level on other patterned planes to form three dimensional power planes. To reduce package capacitance and keep the RC constant low, a personalized reference plane is incorporated. The personalized plane has insulating regions extending at least partially through the plane at predetermined locations that coincide with long signal lines on the wiri…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.