Digital data processing apparatus with pipelined memory cycles
US4866604A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 1, 1988 |
| Grant date | Sep 12, 1989 |
| Priority date | — |
| Expiry date | Aug 1, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2015
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A digital data processing apparatus utilizes a common bus structure for transferring information between functional units, including a processing unit, a peripheral control unit, and first and second memory units. Unit-to-unit information transfers are executed on the bus structure by pipelining signals representative of a transfer cycle that occurs during plural timing intervals and includes plural phases, where the phases of one cycle are non-overlapping and occur in sequence in different respective timing intervals of the transfer cycle. A signalling element periodically generates a first signal indicative the necessity to refresh at least one dynamic memory element in the first memory unit. A memory refresh element normally responds to that first signal for executing a memory refresh cycle during at least one timing interval common to first and second pipelined transfer cycles. A signal is generated indicating the onset of the memory refresh cycle. A memory update element can respond to the update cycle for transferring information from the first memory unit to the second memory unit during a timing interval common to first and second pipelined transfer cycles. The update eleme…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.