Digital multiplying circuit
US4866654A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 22, 1985 |
| Grant date | Sep 12, 1989 |
| Priority date | — |
| Expiry date | Feb 22, 2005 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/724
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A digital multiplying circuit comprises an input terminal serially applied with input vectors which are elements of a finite field GF(2.sup.h), where h is a natural number, an output terminal for producing a signal obtained by multiplying a desired multiplying constant to one input vector, and h multiplying circuit parts each comprising a multiplier and a data selector for selectively producing an input or output signal of the multiplier responsive to an external selection signal. The h multiplying circuit parts are coupled in series between the input terminal and the output terminal, and an r-th multiplier among the multipliers with the h multiplying circuit parts has a multiplying constant .alpha..sup.z, where r=1, 2, . . . , h, .alpha. is a primitive element of the finite field GF(2.sup.h) and z=2.sup.(r-1). At least one of the data selectors within the h multiplying circuit parts comprises a control terminal and is forced to produce a zero output signal responsive to an external control signal applied to the control terminal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.