Error tolerant microprocessor
US4866718A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 25, 1987 |
| Grant date | Sep 12, 1989 |
| Priority date | — |
| Expiry date | Aug 25, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1076
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A microprocessor that detects and corrects random soft errors during program execution occurring in its storage elements (memory). Such a microprocessor utilizes a bit serial architecture and single error correction double error detection techniques that automatically detect and correct soft errors occurring in its internal memory elements during each word cycle. The microprocessor automatically detects and corrects soft errors during each word cycle. The error detection and correction is transparent to the external microprocessor interface. The microprocessor also utilizes a multi-level hierarchical structure which maintains a high instruction execution throughput and also minimizes the number of transistors required for its implementation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.