Quiescent current setting for an amplifier circuit
US4868518A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 31, 1988 |
| Grant date | Sep 19, 1989 |
| Priority date | — |
| Expiry date | Oct 31, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F3/3071
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An amplifier circuit, for example, a class AB output stage, includes a series arrangment of a first transistor (T.sub.1) and a second transistor (T.sub.2), both arranged as diodes, a series arrangement of a third transistor (T.sub.3) and a fourth transistor (T.sub.4) and a series arrangement of a fifth transistor (T.sub.5) and an impedance (R). The first main electrode of the first transistor (T.sub.1) is coupled via the impedance (R) to the control electrode of the fourth transistor (T.sub.4). The first main electrodes of the second and fifth transistors (T.sub.2, T.sub.5) are coupled together and to the control electrode of the third transistor (T.sub.3). The control electrodes of the first, second and fifth transistors (T.sub.1, T.sub.2 and T.sub.5) are coupled together and to the second main electrodes of the first and the second transistor. This circuit provides a small quiescent current in the output transistors using relatively small input transistors (T.sub.1, T.sub.2) and relatively large output transistors (T.sub.3, T.sub.4).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.