Clock signal distribution device
US4868522A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 13, 1988 |
| Grant date | Sep 19, 1989 |
| Priority date | — |
| Expiry date | Dec 13, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0812
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A delay circit is described which automatically adjusts the propagation delay of clock signals, generated by a clock source, distributed to various receiving devices so that the receiving devices are clocked simultaneously. In one embodiment, the clock signal generated by a single clock source is independently delayed for each receiving device. To determine the proper amount of delay, a clock signal is simultaneously transmitted to each of the receiving devices and a clock return signal from each receiving device is returned to a delay circuit via a return path. The delay circuit detects the various differences in round-trip arrival times of the clock signal associated with each receiving device and fixes a particular clock signal delay for each receiving device so that subsequent clock signals will arrive at each receiving device simultaneoulsy.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.