High-voltage pull-up device
US4868620A · kind A · utility
4Cited by
2References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 14, 1988 |
| Grant date | Sep 19, 1989 |
| Priority date | — |
| Expiry date | Jul 14, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/637
Abstract
An integrated circuit in which a large potential can be maintained between the source of the device and the substrate on which this device and other devices are fabricated is described. The circuit employs a minority carrier sink region to remove minority carriers from the gate region of a MOS depletion device. The sink region is shielded from the substrate by a buried layer which prevents punch-through between the sink region and the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.