CMOS RAM with merged bipolar transistor
US4868628A · kind A · utility
10Cited by
6References
9Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 22, 1984 |
| Grant date | Sep 19, 1989 |
| Priority date | — |
| Expiry date | Aug 22, 2004 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/903
Abstract
A CMOS, N-well, P-channel static RAM cell with merged bipolar transistors as its output drivers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.